Techniques to Fix Timing Violation
We know all type of timing path and there timing analysis in Timing Analysis of Paths Part I and Part II. We have covered details analysis of timing paths. Today we are going to cover fixes of timing violation in the design. To understand the fixes of timing violation, we insisted to read once again following topics. So, you will get an idea of timing violation fixes. Timing Arcs Timing Paths Setup and Hold Timing Analysis of Paths Part I Timing Analysis of Paths PartII Let’s see what kinds of timing fixes are…… First, we are taking a look at what are the possible reason behind the violation. Reason for Setup Timing Violation: The combinational logic in the data path has more delay. There is a long net associated data path. More HVT cells are available in the data path. Low drive strength cells are in the data path. There is negative skew like condition between launch and capture clock. Setup time of the capture flip flop is large. Data path migh
