Techniques to Fix Timing Violation

 We know all type of timing path and there timing analysis in Timing Analysis of Paths Part I and Part II. We have covered details analysis of timing paths. Today we are going to cover fixes of timing violation in the design.

 

To understand the fixes of timing violation, we insisted to read once again following topics. So, you will get an idea of timing violation fixes.

Timing Arcs

Timing Paths

Setup and Hold

Timing Analysis of Paths Part I

Timing Analysis of Paths PartII

 

Let’s see what kinds of timing fixes are……

First, we are taking a look at what are the possible reason behind the violation.

 

Reason for Setup Timing Violation:

• The combinational logic in the data path has more delay. 
• There is a long net associated data path. 
• More HVT cells are available in the data path. 
• Low drive strength cells are in the data path. 
• There is negative skew like condition between launch and capture clock. 
• Setup time of the capture flip flop is large. 
• Data path might be routed with the metal layer which has more RC parasitic value. 
• Crosstalk delay slows the data signal due to the adjacent net signal switching in the opposite direction.

 

Techniques to Fix Setup Timing Violation:

Setup violations need to be resolve at both the stage like Synthesis stage and PNR stage. But, fixing of setup timing violation is almost same except few.

• Add a pipeline register on longer data path (only at the Synthesis stage).  
• Break the longer net by adding buffer on the data path. 
• Use LVT or UVT cells by replacing the HVT, but with caution, because they are leakier (more leakage power). 
• Reduce the load the output by cloning, buffering (use progressive buffer is 1x → 2x → 4x …... like that). 
• Increase the drive strength of cells which are used in the data path. It is also called Gate sizing (upsizing or downsizing).  
• Reduce the path delay by logic restructuring and pin swapping. 
• We need to modify the clock tree to get positive skew by ensuring sufficient hold slack in the current path and setup slack in subsequent timing path. 
• Perform the layer optimization by assigning a higher metal layer with less RC parasitic for data path routing. 
• Use the NDR rules to avoid the crosstalk. 
• Replace the existing flip flop with a new flip flop with has less setup time [as a last resort]

 

Reason for Hold Timing Violation:

• The combinational logic in the data is faster. 
• There are LVT/UVT cells available in the data path. 
• Higher drive strength cells are in the data path. 
• There is positive skew like condition between launch and capture clock. 
• Hold time of the capture flip flop is large. 
• Data path might be routed with the metal layer which has lower RC parasitic value. 
• Crosstalk delay faster the data signal due to the adjacent net signal switching in the same direction.

Techniques to Fix Hold Timing Violation:

Hold violations need to resolve at PNR stage. We have to resolve the hold violation at the post-CTS stage because before we do not have clock skew information.

• Delay the data path by adding Hold buffer (delay buffer). 
• Use  HVT cell by replacing the LVT/UVT cells in the data path.  
• Downsize the cell in the data path. 
• We need to modify the clock tree to get negative skew by ensuring sufficient setup slack in the current path and hold slack in subsequent timing path. 
• Perform the layer optimization by assigning a lower metal layer with high RC parasitic for data path routing. 
• Use the NDR rules to avoid the crosstalk. 
• Replace the existing flip flop with a new flip flop with has less hold time [as a last resort]

 

There are some other violations which are related to transition, capacitance and fanout. We will see this violation in our next post.

 

At this note of discussion, we wrapped this topic and we will meet soon with a new topic. Thank You, Have a nice day!!!