Timing Arcs

A timing arc represents the timing relationship between pins of logic cells.  The timing information for the timing path is provided through a timing arc. The STA tool used timing arc to generate delays of the cell. A cell has multiple timing arc. There are two types of timing arc – 

1. Delay arc 
2. Constraint arc. 

The delay for the timing arc through the cell (e.g. here is Inverter) is dependent on two factors: 

1. The output load which is capacitance load at the output pin of the cell 
2. The input transition time (slew) of the signal at the input.

While calculating the delay of a cell, we required input slew and output load. Any variation in load and slew leads to the different delay value. There are a number of delay model used to calculate the delay of the cell such as NLDM. The delay of the cell is available in the liberty file which is generated by the process of characterization. We will discuss liberty file in DESIGN SETUP section.

There are two types of timing arc

Delay Arc

Delay consists of cell delay arc and net delay arc. Cell delay arc represents the propagation delay between an input and output pin of the cell. Net delay arc represents a delay of the net due to parasitic.

Constraints Arc

The arc which is associated with a sequential cell is called constraint arcs. Constraint arc is defined for input pin or between input pins. In constraints are Setup arc and Hold arc are defined between input pins (CLK and D) of a flip flop. Minimum pulse width arc defined for input pin of a flip flop.

 

Timing arc for Inverter

It has 4 timing arc

• Rise time at pin Y 
• Fall time at Pin Y 
• Propagation delay low to high from A to Y 
• Propagation delay high to low from A to Y

Timing arc for AND gate

It has 6 timing arc 

• Rise time at pin Y 
• Fall time at Pin Y 
• Propagation delay low to high from A to Y 
• Propagation delay high to low from A to Y 
• Propagation delay low to high from B to Y 
• Propagation delay high to low from B to Y

Timing arc for D flipflop

It has 10 timing arc – 4 delay arc and 6 constraint arc.

Delay arcs  

• Rise time at pin Y 
• Fall time at Pin Y 
• Propagation delay low to high from CLK to Q 
• Propagation delay high to low from CLK to Q. 

Important to note that there is no delay arc between D to Q pin

Constraint arcs 

• Setup arc when D is rising for D to CLK pin  
• Setup arc when D is falling for D to CLK pin 
• Hold arc when D is rising for D to CLK pin 
• Hold arc when D is falling for D to CLK pin 
• At CLK pin, Minimum pulse width for high  
• At CLK pin, Minimum pulse width for low

 At this note of discussion, we wrapped this topic and we will meet soon with a new topic of STA. Thank you. Have a nice day!!