Latch-up and its prevention in CMOS

Latch-up and its prevention in CMOS

By Keith Sabine

Early CMOS processes suffered a reliability concern that became known as latch-up. It resulted in circuits either malfunctioning or consuming excessive power, and could be either inherent in the design or triggered by voltage spikes on IO pads that could forward bias PN junctions they were connected to.

 

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