Process Variations

As we have discussed PVT in the previous post, wherever we discussed before on PROCESS in PVT topics, it just small overview, we can say. Today, we are going to discuss more on Process variation.  

 

Integrated circuits ICs are manufacturing in large volumes called batches. During the manufacturing process, the size or structure of transistor throughout the die is not uniform. Due to this, transistor gets fabricated with fast or slow switching during the manufacturing is called Process.

During manufacturing, transistor and interconnect have variation in oxide thickness, layer thickness, lateral dimensions and doping concentration. These variations are classified as follows:

Intra-Die: The variation which occurs on a die called a local variation. For example, one transistor might have a different parameter, such as threshold voltage, than its adjacent transistor due to non-uniform distribution of dopant atoms implantation.

Inter-Die: The variation which occurs on different dies called a global variation. For example, all transistors on one die might be narrower or shorter than normal because they were etched more than the other die.

 

Process Variation in Devices:

The impact of process variation is more on the channel length and threshold voltage.

The channel length variations are caused by photolithography proximity effect, deviation in optics and plasma etch dependencies.

The threshold voltage variations occur because of different doping concentration and annealing effect, mobile charges in the gate oxide, and discrete dopant variations caused by the small number of dopant atoms in tiny transistors.

Process Variation in Interconnects:

The interconnect process variation has changed the dimension of layers and thicknesses of the design. The changes in line width and spacing, metal and dielectric thickness, and contact resistance are affected most on the design. The variation in line width and spacing, like channel length, is caused by the photolithography and etching proximity effects. Also, the thickness is varied due to polishing. The contact resistance depends on contact dimensions and the etch and clean steps.

Process variation can be classified as follows:

• Lot-to-lot (L2L) 
• Wafer-to-wafer (W2W) 
• Die-to-die (D2D), inter-die, or within-wafer (WIW) 
• Within-die (WID) or intra-die

Wafers are processed in the batches called lots. One wafer may be exposed, for a slightly different amount of time than another, to an ion implanter causing W2W variation, like a variation in threshold voltage. A die near the corner of the wafer may etch slightly differently than a die in the centre, causing D2D variation, like channel length variation. D2D variations ultimately make one chip faster or slower than another one. Such variations can be handles by providing enough margin to cover 2σ or 3σ  of variation and by rejecting the small number of chips that fall outside this bound. WID variations were small compared to D2D variation. WID variations are more challenging to manage because of some billons or millions of transistors on a chip.

In summary, transistors on the same die match better than transistors on different dice and adjacent transistors match better than widely separated ones.

 

At this note of discussion, we wrapped up this topic and will meet with a new topic of STA. Thank you. Have a nice day!!!!