Process - Voltage - Temperature PVT

In STA, we have to analyse the design performance in all operational modes and cases to work in all possible condition. Typically, we checked the performance of design at a specific operating condition called as PVT, Process, Voltage, Temperature. The chip must be worked, e.g., in all possible condition like in extreme cold or extreme hot condition, and/or throughout voltage range. These conditions are called corners. Cell delays are calculated based upon variation of these three parameters.

So, what is actually PVT?????

Process:

Integrated circuits ICs are manufacturing in large volumes called batches. During the manufacturing process, the size or structure of transistor throughout the die is not uniform. Due to this, transistor gets fabricated with fast or slow switching during the manufacturing is called Process.

The variation in the transistor happens due to non-uniform fabrication of layer (oxide and metal) throughout the die. Such variation is gradual. The size and shape of the layers are differing. Oxide thickness variation and doping concentration variation also affect the process.

Process variation is more dominant in lower node technologies.

Figure: PVT vs Delay

Voltage:

As we move towards the lower technology nodes, the power requirement is also reduced. The supply voltage is also an important parameter to get a delay of a cell. The supply voltage is not constant throughout the chip and hence the delay of the cell varies in a chip.

An IC is expected to work over the range of supply voltage (Vs) consider +/- 5% (or  10%) of the supply voltage. Transistor should be switch at high voltage (Vs + 5%) and at a lower voltage (Vs - 5%) and it results in faster switching – less delay and slower switching – more delay respectively.

The variation in the voltage is due to IR drop which is caused by parasitic RC.

Temperature:

An IC also works over the range of temperature. Transistor should be switch at a cold, normal and hot temperature. For the higher technology node, the temperature has linear variation but for lower technology node (DSM), the temperature has an inverse variation graph. Such contrary behaviour is called Temperature Inversion.

Delay is directly proportional to R and C. It means that delay is inversely proportional to I_DD  and directly proportional to Load (C_out).  

At higher technology node, the design is significantly working on the higher supply voltage. The current I_DD is directly proportional to the carrier mobility (µ) and factor (V_gs – V_th)².  At the higher supply voltage, the effect of  (V_gs – V_th)² is significantly less. So that the variation in current I_DD is proportional to µ, carrier mobility. Hence, when the temperature rises, carrier mobility is decreasing and as a result, the delay of the cell will increases.

So, at higher technology node, as temperature increases delay also increases.

At lower technology node, the design is working on lower voltage, lower V_gs and V_th. The current I_DD is directly proportional to the carrier mobility (µ) and factor (V_gs – V_th)².  At the lower supply voltage, the effect of  (V_gs – V_th)² is significantly more over the carrier mobility, µ. The difference of (V_gs – V_th) is small and the square of the term further smaller and its significantly reduces the I_DD current.

Now, at the lower voltage and lower temperature, current reduces due to the (V_gs – V_th) and as a results delay increases even at a lower temperature.

So, at lower technology node, as temperature decreases delay also increases. This phenomenon is called Temperature Inversion.

 

This PVT variation leads to the variation in the delay of the cell. There are three cases or corner where we check our design such as worst case, normal case, best case. In the worst case, the process is slow, voltage is low and the temperature is high whereas in best case process is fast, voltage is high and the temperature is low.

If PVT variation occurs across multiple dies, then it called global variation.

If PVT variation occurs over a single die, then it called local variation.

Overall, it is possible that two region of the same chip are not identical PVT condition. These differences case rises due to many factors such as- 

• IR drop variation along the die area affecting the local power supply
• Voltage threshold variation of the PMOS or the NMOS device due to non-uniform distribution of oxide thickness.
• Channel length variation of the PMOS or the NMOS device due to non-uniform doping concentration.
• Temperature variation due to local hot spots.
• Interconnect metal etch or thickness variations impacting the interconnect resistance or capacitance.

Local variation can be resolved by OCV, AOCV and POCV. We will discuss it more in the respective post.  

 

At this note of discussion, we wrapped this topic and we will meet soon with a new topic of STA. Thank You. Have a nice day!!