Timing Exceptions - Multicycle Path

As we have in the previous article, we discussed the Timing Exceptions – False Path and, Min & Max Delay Path. Today, we are going to complete our discussion on the timing exceptions.

Multicycle Path:

As we have seen timing analysis of various paths, usually, data needs a cycle or half-cycle to evaluate itself and getting captured by capture flip flop. But there may be the cases where the paths need more cycle to evaluate themselves. 

In some cases, the combinational data path between two flip-flops can take more than one clock cycle to propagate through the logic. In such cases, the combinational path is declared as multicycle paths.

Even though the data is being captured by captured flip flop on every clock edge, we direct STA tool that the relevant capture edge occurs after the specified number of clock cycles by defining or constraining in SDC file.

*Figure: Multicycle Path

In the above example, combinational logic needs 3 clock cycle to compute the data and correctly captured by capture flip-flop. We configure this path by the following instruction/commands:

set_multicycle_path -setup 3 -from [get_pins UFF0/Q] -to [get_pins UFF1/D]

set_multicycle_path -hold 2 -from [get_pins UFF0/Q] -to [get_pins UFF1/D]

By constraining the path to be a multicycle path, we instruct the STA tool that where we have to check the setup (-setup 3) and hold (-hold 2) value for that particular path. In the above example, the value after setup and hold has significance.

Now, in first instruction where we define value for setup check i.e. 3. Its means, we instruct the STA tool that setup will check after 3 clock cycle. For example, of clock period is 2ns, the setup will check at 6ns.

But the real game is different. What about the HOLD check!!!

*Figure: Multicycle Path: Setup and Hold Checks

 

In most common scenarios, we would want the hold check to stay as it was in a single cycle setup case. Even for hold check in normal single cycle path, we check the hold at the same clock edge cycle. In other words, the default hold check is to be done on the active edge prior to the setup capture edge.

For the hold check understanding for a single clock cycle, I used to give the same context in a different form. Because the understanding of hold check in the multicycle path is difficult to understand.    

Now, the data is free to change anywhere in between the three-clock cycle. The hold checks in the multicycle path, without specifying the hold value, the check is done at edge prior to the setup capture edge i.e. at 4ns by default. But it is not intended. We need to be checked the hold check at the same edge where we launched the data i.e. at 0ns.

By specifying the hold value in the multicycle path, we instruct the tool that hold must be check at the same point of time where data has launched. We need to move the hold check 2 cycle prior to the default hold check edge and that's why hold check 2 is specified. By doing this, we get the intended behaviour of hold check as we get in the normal case.

Thus, a multicycle path setup specified as N (cycles) should be accompanied by a multicycle hold constraint specified as N-1 (cycles).

 

At this note of discussion, we wrapped up this topic and we will meet soon with a new topic of STA. Thank you. Have a nice day!!!