Timing Exceptions – False Path and, Min & Max Delay Path

Till now, we discussed Typesof Timing Analysis and Introduction to STA, we have seen the term TIMING EXCEPTION. Today, we talked about the same.

 

As we have seen DynamicTiming Analysis and Static Timing Analysis, each has its own advantages and disadvantages. Each timing analysis dominated one another in one or other ways and STA is widely used to analyse timing.

Performing STA throughout the flow is widely used but it has some exception. It is possible that some paths don’t perform anything in terms of functionality or the case where one path needs more time to evaluate before it going to capture by flipflop.

Timing exception provides a means to suppress the reporting timing for a specific path. These exceptions need to defined in constraints (in SDC file). By doing this, we will have focused on actual timing violations.

There are three types of Timing Exception:

• False Path 
• Multicycle Path 
• Min & Max Delay Paths

 

False Path:

It is possible that certain timing paths are not operational in the actual functional operation of the design and such cases were arises in the design where paths are passing through the MUX. So, the path which is physically existed in the design but functionally is not valid, such paths are called False Path.

Such paths are doesn’t get reported in the DTA and can be turned off during STA analysis, otherwise, it will get reported. That’s why we have to constrain such paths in SDC file.

The advantage of determining or identifying false paths is that the analysis space is reduced, thereby allowing the analysis to focus on actual paths. It leads to reduce run time.

Figure: False Paths

set_false_path -from [get_ports A]-through [get_pins M2/D]

set_false_path -from [get_ports B]-through [get_pins M2/E]

In the above example, the path from A – C – D – F the logical path never exist. Similarly, the path from B – C – E – F the logical path never exist. That’s why we configured these to be the false path.

 

Minimum & Maximum Delay Path:

The min and max delay paths are constrained in SDC file for the specific path which requirement without defining a clock. In short, we defined Min and Max delay for the path which doesn’t require the clock.

We can define the min and max delay for

• In2Out path or combinational path 
• Paths across asynchronous timing groups

Figure: Combinational Path

set_max_delay -from [get_port A] -to [get_port B] 1.1

set_min_delay -from [get_port A] -to [get_port B] 0.6

 

Only one exception is left. We will discuss Multicycle Path in the next article.

 

At this note of discussion, we wrapped up this topic and we will meet soon with a Timing Exception – Multicycle Path. Thank you. Have a nice day!!!