Introduction to STA

Hi readers, today, we are going to discuss the overview of the STA procedures for nanometer design and try to address questions like what and why and here we go ………………

 

STA is one of the timing analysis technique where we check whether a design meets its performance goals of digital design or not. The STA is static which means output response of the design is not depended on any input values. A given design along with the number of inputs signal likes data, clock, user-define and others, the purpose of STA is to validate the design, whether design can operate under the specified goals.

In STA, design under analysis verify the hold and setup timing checks, analyse timing exceptions, verify the for each timing paths, verify constraints of design and at the end, we will find out the reason behind failures of the timing paths. In short, STA ensures the availability and credibility of data launch and capture. The more important aspect of STA is that the entire design is analysed once and then we make changes, and once again we have to perform analysis.

To perform STA of design, we have to set external environments such as input external delay, output external delay, clock definition, timing exception and some other parameters need to be specified. These parameters are specified in the standard format called SDC (Synopsys Design Constraints) in TCL format.

We will discuss more on the SDC file under the title of ‘Design Setup’ later.

The key-notes and limitations of STA were already discussed in the previous post of “Types of Timing Analysis”.

Figure: STA checks in Digital Design Flow ¹

Any design in the world is not ideal. Design functionality and performance due to crosstalk and noise. The noise occurs due to crosstalk with other signal nets. It limits the frequency of design operation and it leads to failure of functionality.

We have to perform STA right from synthesis till at end of signoff stage. STA is run at RTL level to check the functionality of the design against the timing. Once RTL design is synthesized to get GLS, again have to run STA on mapped and optimized GLN to identify worst or critical timing paths in the design. At each stage of physical design, we have to perform STA to analysed the reason for failures and there way out.

At the first step of physical design, we assign an entire clock to be ideal, so that we can focus on the data path first. After floorplan stage, we have to perform STA to check whether netlist which we have is good or bad. Also, we have to check the constraints of the design specified in the SDC file is correct or over constraint. This process is called a Zero wire load model. Along with it, we get violated timing paths and we have to fix those paths. Again, after the placement stage, we have to perform STA, some paths may get fixed and somewhere arise new violation due to congestion.

At CTS stage, we actually route clock tree and get a partial layout of our design. This stage of STA analysis will give us the reason for timing violation due to long clock nets or more RC value of net or crosstalk or congestion. After the final detail routes of nets at routing, the stage gives a clearer picture of the layout. STA analysis reports violated path due to more RC values of net and effects of coupling. We extracted RC value of design and send to synthesis team to analyses timing (the process called as Back-annotation) and it will release new updated GLN.

To summarized our discuss, STA is performed at the logical level and physical design phase. At the logical level, STA can be carried out using ideal interconnect and ideal clock with estimated skew value in clock uncertainty. In the physical design phase, STA can be performed using ideal interconnect and clock, routed interconnected nets, clock trees and actual inclusion of the effect of crosstalk.

 

At this note of STA, we wrapped up this discussion and we will meet soon with a new topic of STA. Thank you and Have a nice day !!

¹Figure is taken from the book “ Static Timing Analysis for Nanometer Design” by J. Bhaskar and Rakesh Chadha