ASIC Design Flow (Part- II)

Today, we are going to discuss the continuation of our previous post ASIC Design flow- part I. In this post, most of the heading we will discuss again in their respective titles. Let's complete our discussion on the ASIC Flow.........

Design for Testability

Design for testability (DFT) is a design technique that adds extra logic in the design to check/test IC from manufacturing defects. DFT ensure the quality of end design so that only good design move to consumers. Automatic test equipment (ATE) is used to test chip.

During the fabrication of a chip, a device with defects may be manufactured due to causes of contamination in the substrate, properties of interconnect metal, process variation, ununiform oxide layer and many more. It’s lead to open and short in interconnects or in the internal structure of transistor and many more.

There are various types of manufacturing tests such as scan chain, BIST and more.

We will discuss more on DFT in the Placement section of the blog.

Logic Equivalence Checks

At this stage of LEC is called as Pre-layout LEC.  LEC is the process of matching or checking GLN, which generated from synthesis, with RTL code of design. After the synthesis, the netlist is the new representation of the design. Before moving ahead, we have to clear this check.

Pre-layout STA

Static timing analysis (STA) is a kind of timing analysis technique where we check whether a design meets its performance goals, which are normally expressed in terms of maximum propagation delay or minimum operating frequency. STA refers to the process used to verify timing of the design without the need of input stimuli. It is a very fast and exhaustive process and suitable for a large design.

STA itself is a subject. We will discuss more on it in our STA section of the blog.

At this stage, we have to analyze report timing by giving input of Verilog code, timing library and technology library. If the design goal meets, we can move to APR, otherwise, go back to synthesis to make further changes. 

Automatic Place and Route

APR is the process of generating the layout of the chip from GLN using APR tool. Design a layout such that it meets the design goal such as performance, power, area (PPA). In APR, the following steps are involves –

• Partitioning 
• Floorplanning 
• Power-planning 
• Placement 
• Clock Tree Synthesis 
• Routing

We will discuss more on all these steps elaborately under their respective titles.

The required inputs and outputs to the APR are shown below and at the end of it, we get GDSII (Graphic Design System version II) along with the timing reports.

* Inputs and Outputs to APR*

Post Layout LEC

At this stage of LEC, LEC is the process of matching or checking GLN, which generated from APR (called extracted netlist), with Netlist from synthesis.

LEC, overall, does verify functional correctness and not a design specification. While processing LEC, it does not accept any input and it gives completely ensured to designer from its result.

Parasitic Extraction

The process of extracting interconnect parasitic R and C values from the actual layout is called parasitic extraction. Interconnect parasitics are stored in a standard format such as SPEF file, Standard Parasitic Exchange Format. There is another file SDF, Standard Delay Format, used during the back-annotation process to analysis timing of design after lay down the actual layout.

We will discuss more on it under the umbrella of STA.

Post Layout STA

This stage of flow is similar to pre-layout STA. But the only difference is that at this stage we have to give parasitic information as one of input to STA tool to get timing report. We use those reports for further analysis.

Physical Verification and DFM

After the design layout is completed, the layout must be verified to ensure the correctness of electrical and logical functionality.  During the physical verification of design, we check whether the layout of the design is followed design rules or not, also checks whatever we drew using the APR tool is matched with the schematic of the design. For that purpose, we resolve all DRC and LVS and ERC error, once the final layout is done.

DFM, design for manufacturability, checks ensure our yield of the chip.   

We will discuss more on PV, DRC, LVS, ERC, DFM under the umbrella of Sign-off Checks.

Fabrication

Once the layout of the design clean with DRC, LVS, ERC, we will send GDSII file to fabrication company for manufacturing chip. The handoff of the design to a manufacturing company is called tape-out.

At this note of discussion, we wrapped up ASIC Design Flow and we will meet soon with a new topic of physical design. Thank you, Have a nice day!