ASIC Design Flow (Part- I)
Today, we are going to
discuss ASIC Design flow and their subsequent steps. Our main focus of the blog
is the Physical design step of ASIC flow. Before move towards the actual work
of physical design, we can get an overall perspective of ASIC Flow. And, here
we go……………
A typical VLSI design
cycle starts with design specification follows a series of steps and eventually
produces a packaged chip. A Typical ASIC Design flow may be represented by a flow
chart shown below. From the design specification to RTL Verification is part of
RTL Design Engineer (called as Front-end Engineer). From APR to Sign-off stage
is part of Physical Design Engineer (called as Back-end Engineer).
Our main emphasis on
Physical Design step. However, to get a global picture of flow, we briefly
outline the steps of the ASIC design flow.
Design Specification
The step of any design
process is to lay down the specification of design from the market required document
provided by the company. The designer defines the overall goals and high-level
requirements of the system. The factors to be considered in this process
includes the performance, size of die, functionality, power, technology node,
operating frequency.
- Brief description of functionality.
- Sub-block and block-level functional of the design.
- Timing relationship with all ports and blocks.
- Pin and port placement along with direction, the function of each pin and port.
- Detail Functional description of each and every block, sub-block and their connection of the design.
- Illustration of architecture from the point of view of a programmer.
- Package information for top-level design chip. Foundry and technology-related information.
RTL Design team used these
design specifications to implement the functionality of the the design.
RTL verification team
used these design specifications to create test cases which needed to check the
design.
Architecture
By using design
specification, a basic chip architecture must be determined to meet the design
specification. The entire chip is divided into blocks and sub-blocks called
microarchitecture. The architecture of design is decided on many factors such
as –
- Power requirement.
- Choice of process technology and layer stacks.
- Usage of hard and soft IP blocks internal and external communication of blocks.
- Memory management and addressing scheme.
- Pinout, package and die-package interface.
Microarchitecture blocks
or sub-blocks contains information of interface information; blocks
functionality in terms of state machines, algorithm, exception and more; Timing
diagram and the relationship between /among signal associated with sub-block.;
Power management strategies.
RTL Design
Today, the design has a large
number of inputs and outputs, and timing relationship among them. Logic design
is performed at RTL (register transistor level) using a hardware description
language such as VHDL or Verilog by means of a program that define
functionality and timing behaviour of the chip. The behaviour aspects of the
design are considered without implementation specification information.
A digital system is said to
be represented at the register transfer level if is specified –
- Register
- The operation performed on data stored in registers
- Control logic to decide when to operate on the data.
RTL design technique is a
very popular method used by companies. It is suitable large design logic using
structural, behavioural and dataflow abstraction. RTL model deals with
synchronized data flow among various sun-block units.
Once RTL code is ready,
we simulate that code using RTL simulator. Simulation interprets and analyzes
the code to produce graphical output like waveforms which helps in debugging
the design.
RTL Linting is a process
that used to determine synthesizability of RTL code. linting use to simulate
structural analysis to verify the quality of RTL code that prevent synthesis
issues and functional error or bug.
RTL Verification
RTL verification is the iterative
process of simulating design using a testbench. RTL verification team used
design specifications document to create test cases which needed to check the
design and response from testbench against the specification. Approx 60-70% of
design time of engineering resources work on RTL verification. This is because of a high number of valid scenarios
and features to tested in simulation and verified before RTL code translated
into Gate level Netlist (GLN).
Synthesis
Synthesis is a process of
translating RTL code to gate-level netlist (GLN) using the EDA tool. Synthesis
tool is computer software that performs logic synthesis of RTL code and tool
optimized and mapped design to a target library to generate a technology-specific
GLN. As the synthesis process progresses, more details are added in the design.
Synthesis is performed in three-step –
- Translation: Logical part of RTL code is realized into the component by using GTECH library. Arithmetic operation is realized into the component by using Design Ware library.
- Mapping: In mapping, Boolean function realized into the component by using technology library.
- Optimization: It is performed at end to optimized the design on the bases of time, area, power and design rules.
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