ZERO WIRE LOAD MODEL

Today we are going to take a look at a timing model which are used as a sanity check before to start the step of physical design.

 

ZERO WIRE LOAD MODEL is the kind of timing model which checks the timing of the design without any kind of parasitic information i.e. zero load. ZWLM is performed at different stages such as after synthesis, test insertion stage and before to physical design.

In ZWLM, cell delays are picked from standard cell libraries to perform timing checks.

During the PNR stage, we perform ZWLM before floorplanning or before powerplanning.

Why ZWLM?

ZWLM is used to check the quality of Netlist and Constraints specified in SDC File. Ideally, zero wire load timing checks should be clean setup violation; hold violation should be under control because the tool is not aware of the actual position of the cell.

If ZWLM timing checks are zero then we can guarantee the quality of netlist and constraints. But ZWLM timing checks are not clean, then we have to double checks the constraints.

Setup violation in ZWLM must be zero and small (in term of value) hold violation is acceptable. But large hold violation also pointed something wrong in constraints. Violation in the asynchronous timing path is not considered.

 

 

At this note of discussion, I wrapped up this topic and we will meet soon with a new topic of floorplanning. Thank you. Have a nice day!!!!