Floorplanning

Hi readers!! Today, we are going to give a start to discuss the first step of physical design i.e. Floorplan. And here, we go …………

 

Floorplanning is the most difficult and important step in physical design or we can say that floorplanning is an art of physical design. A well-thought-out floorplan leads to a design which higher performance and optimum area. 

There is a more step, before the floorplan, is PARTITIONING. In this step, design divided into particular shapes called a block. The block on which we perform APR called Block-Level Design.   Partitioning is not the scope of this article.

After the circuit partitioning phase, means the entire design divide into blocks and sub-blocks, the actual floorplanning of the layout starts. In the floorplanning, we have to estimate the area which can be utilities by the blocks and sub-blocks. In addition, the netlist specified connection must also be available.  

Floorplanning can be challenging in that it deals with the placement of IO pads and cells as well as Powerplanning at block and chip level. Before proceeds with floorplanning, the designer needs to make sure that the data used during the course of floorplan must be ready properly. Otherwise, we will see repercussion in the middle of flow i.e. at the end of a placement with unresolvable congestion.

The arrangement of standard cells and macros cell are performed in two-phase – Floorplan phase and Placement phase. In the floorplan phase, we are placed all memory cell i.e. macro cell in three different manner- Abutted, Non-abutted, and Partial Abutted floorplan. In the placement phase, we are placed standard cells in core contiguous area which is created at the stage of floorplan.

Usually, the shape and size of the block are decided at the partitioning stage. Initially, the size of the block is not fixed. We can achieve the estimated size of the block on a number of iterations. There are number of algorithms associated with floorplanning to place macro cell at block-level and blocks at the chip level.

In floorplanning, several Macros, Physical cell (layout of cell in .lef file) are placed in the block in such way we can get core contiguous area for placement of standard cells. Once we have done with floorplan then we have to do powerplanning for that particular block and subsequently to the chip. We will discuss more on each aspect and step of floorplanning in detail manner in the next post.

The types of data required to start floorplan are gate-level netlist, technology file, physical and timing library, and constraints. Each of these files covered under Design Setup.

 

At this note of discussion, we wrapped this and we will meet soon with a new topic of floorplanning. Thank you. Have a nice day!!