Cell Characterisation

Today, we are going to see the process of characterisation to generate Liberty file. Characterisation itself is a subject like STA. Here, we are going to discuss the just overview of cell characterisation in order to understand about liberty file, characterisation flow and some parameters which are repeatedly used while configuring the design.

 

Introduction

In the STA, we need a delay of the cell to analyse the timing of the design. The delay of the cell is available in Liberty File (.lib) which is provided by library vendor. We can generate the Liberty file by a process called characterisation.

The RTL code simulator needs to have the process-specific description of each logic function in the library, such as rise time, fall time, propagation delay, etc. for multiple circuit conditions of loads and input slews. Along with this information, we need some device parameters and physical representation of each gate are collectively known as the standard cell library. While synthesis, the tool need to have access to this standard cell library information which is obtained by the process called characterisation*.

The parameters obtained for each GATE during characterisation:

• Delay Table and Skew Table for wide range of PVT by variable input slew and output load. 
• Input pin capacitance. 
• Power consumption for each cell. 
• Logic function of each cell.* 
• Speed of cell under different input slew and output load.* 
• For sequential cells, setup time and hold time table is also available for different input slew of data and clock pin.

 

Reason for Characterisation

Digital design implementation, i.e. RTL-to-GDSII, goes through several design steps like analysis (like simulation, verification, timing, power, etc.), physical design implementation and fixing (timing, ECO, rule fixing, etc.). These design steps are performed using EDA tools, which is dependent on cell modules. It means that cells and their models play a vital role.*

Now, if we delay, skew, power, logic function, etc. of each cell, then it is very difficult to get all those parameters. So, to get these parameters for standard cell in polygon format, i.e. at GDS format, is very difficult and that is* –

• Extraction of functionality is complicated. 
• Functional or delay simulation takes more time. 
• Power extraction for the whole chip takes more time. 
• Calculation of timing constraints are very difficult.

Then, the solution to this problem to generate a model for delay, function, constraints, power, etc.  on cell/gate level called cell characterisation.

Therefore, availability of characterized model of a cell is the only economic way to implement a digital chip.

Characterisation Flow:

Cell characterisation is the process of analysing a [standard cell] circuit using static and dynamic methods to generate cell model by extracting the information and convert into the proper format for full-chip implementation flow.

*Figure: Typical Characterisation Flow

 

The typical characterisation flow*:

1. Input processing 
• Read spice models 
• Read spice netlist
• Read other inputs like temperature, voltage, etc. 
2. Cell function 
• Recognition 
• Acquisition 
• Specification 
3. Stimulus generation 
4. Circuit Simulation and measurement 
5. Model generation and Verification

 Characterisation Parameters*:

Global parameters

• PVT Corner selection 
• Unit definition 
• Threshold values 
• Limits of max output load, max transition time, etc. 
• Wireload models

For Mapping, Functional Simulation

• Functionality

For Optimization, Delay Simulation

• Area 
• Power 
• Timing Constraints (Setup/Hold time, Recovery/Removal time) 
• Propagation delay

For Power Extraction, IR-Drop Analysis, EM Analysis

• Dynamic power (Switching power & Internal Power) 
• Static power (Leakage power) 
• Passive power (Internal Power)

For Place and Route

• Geometry (Cell Width) 
• Pin Locations 
• Routing channels (metal areas not used by a cell) and routing obstructions (additional metal areas used by cell)

 

 

Note: While writing this article, the content and figure are taken from books, online pdfs, presentations and websites. I enlisted those under the heading *References. Please take a look.

 

At this note of discussion, I wrapped this topic and we will meet soon with a new topic. Thank you. Have a nice day!!!