Signoff Checks

Today, we are going to take a look at signoff checks of design. Verification of the design is an important phase of physical design. We have to send error-free GDSII to fab for fabrication. In this post, we will take look on it and here, we go…………………

 

After the routing, the layout of the design is completed. Now, we have to check the polygon (mask), which are completed, according to rules specified by the foundry.  At this stage of signoff checks, we have to perform the following checks -

1. Physical Verification.
2. Timing Analysis. 
3. Logic Equivalence Checking.

We will take a look at these signoff checks. Timing analysis is covered under STA. The other two topics such as LEC discuss here and Physical Verification in brief. We will discuss more on Physical Verification in a separate post.

LEC

After completing the layout of the design, this LEC is called as post-layout LEC. The LEC is the process of matching or checking GLN, which generated from APR (called extracted netlist), with the Netlist from synthesis. LEC, overall, does verify functional correctness and not a design specification. While processing LEC, it does not accept any input and it gives completely ensured to designer from its result.

The Input to LEC is GDSII and Netlist, after synthesis, and get the result in term of the match it or not. We can give input to LEC as GLN and RTL, or RTL and RTL, or GLN and GLN.

Physical Verification

Physical verification is the process whereby an IC layout is verified to ensure correct electrical and logical functionality and manufacturability. We have to perform a different type of verification checks such as DRC, LVS and ERC.

In DRC, we have to check the dimension of polygons in compliance with rules specified by the foundry. We required GDSII file and DRC rules from foundry as inputs and we will get DRC summary report, log file and DRC error database. Basically, there are four types of DRC- Interior, Exterior, Extension and Enclosure.

In LVS, once DRC has done, then we have to match our GDSII (layout extracted netlist) with the original schematic. It doesn’t ensure the functionality of the layout. We required spice file, GDSII file, Pad reference file and LVS rules from the foundry and we will get LVS summary report, extracted netlist and log file. In LVS, checks follow the three process such as Extraction, Reduction and Comparison.

ERC, Electrical Rule Checks, check the overall electrical integrity of the design. Means, ERC reports those error which causes a problem to the design. In ERC we have to perform certain checks such as – any floating N-well or substrate; check the connection of N-well and substrate of the tap cell to VDD and VSS respectively.

 

 

At this note of discussion, we wrapped up this and we will meet soon a new topic of signoff. Thank you and have a nice day!!