Physical Design

Today, we are going to discuss physical design briefly. We will learn more on this subject later one by one under a different heading. And here we go…………

In the Physical design, all design components in the design are instantiated with their geometric representations. In other words, all polygonal shapes of each and every standard cell, memory unit, interconnect, etc., which are fixed in their shapes and sizes during physical design steps. Once we are done with it, then GDSII file is released for tape-out.

The physical design has two major parts, one, derives a layout for a netlist and another involves analysis and tuning of a design characteristic. Physical design is performed as per the design rules prescribed by the foundry that represent the physical limitation of the fab process. Physical design directly impacts on various factors of design such as area, performance, power and more. We will see these with the examples –

Area: placing the cell far apart leads to long interconnect and it will impact on the delay between the cells.

Power: transistor with smaller gate length switches faster at cost of higher leakage current.

Reliability: a large number of vias can reduce the reliability of the design.

Performance: longer nets have significantly more delay of the signal.

Yield: while routing nets, routes may place near to one another and it will create EM related issue. Open shorts might happen during manufacturing. Also, longer nets undermine yield and has a higher possibility of open.

Physical design of a project (chip) is performed in several stages. –

Partitioning

In DSM technology, netlist of a design is longer. We break up netlist into several parts called blocks. We perform physical design steps on the block-level and at the end, we integrated blocks into a chip.

Floorplanning

Floorplanning determines the position of macros and IO cell and defines the region for the placement of standard cells.

Powerplanning

Powerplanning provides the power connection to each cell macros from an external power supply.

Placement

Placement provides automatic placing of standard cell in the region which was provided at the stage of floorplanning.

Clock Tree Synthesis (CTS)

CTS connects the clock pin of the sequential cell to the clock source in order to minimize clock skew.

Routing

Routing lays down detailed interconnect metal wire from pin to pin. While doing it, tool take care DRC, LVS and timing constraints.

 

At this note of discussion, we wrap up this topic and we will meet soon with a new topic of STA. Thank you, Have a nice day!